Infineon Technologies TC1796 User Manual

TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges
User’s Manual 6-46 V2.0, 2007-07
Buses, V2.0
DMAH 4rwDMA Grant Trigger Enable, High Priority
0
B
FPI Bus transactions on SPB with low-priority
DMA channels as bus master are enabled for
grant trigger event generation.
1
B
FPI Bus transactions on SPB with low-priority
DMA channels as bus master are disabled for
grant trigger event generation.
LFI 5rwLFI Bridge Grant Trigger Enable
0
B
FPI Bus transactions on SPB with LFI Bridge as
bus master are enabled for grant trigger event
generation.
1
B
FPI Bus transactions on SPB with LFI Bridge as
bus master are disabled for grant trigger event
generation.
DMAL 6rwDMA Grant Trigger Enable, Low Priority
0
B
FPI Bus transactions on SPB with high-priority
DMA channels as bus master are enabled for
grant trigger event generation.
1
B
FPI Bus transactions on SPB with high-priority
DMA channels as bus master are disabled for
grant trigger event generation.
CBL 7rwCerberus Grant Trigger Enable, Low Priority
0
B
FPI Bus transactions on SPB with low-priority
Cerberus as bus master are enabled for grant
trigger event generation.
1
B
FPI Bus transactions on SPB with low-priority
Cerberus as bus master are disabled for grant
trigger event generation.
0 [31:16] r Reserved
Read as 0; should be written with 0.
Field Bits Type Description

Infineon Technologies TC1796 Specifications

General

Brand	Infineon Technologies
Model	TC1796
Category	Controller
Language	English