Infineon Technologies TC1796 - Page 340

TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges
User’s Manual 6-47 V2.0, 2007-07
Buses, V2.0
RBCU_DBGRNT
RBCU Debug Grant Mask Register (34
H
) Reset Value: 0000 FFFF
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
1
DMA
L
1
DMA
H
1
rw rw rw rw rw
Field Bits Type Description
1 [3:0],
5,
[15:7]
rw Reserved
Read as 1 after reset; reading these bits will return the
value last written.
DMAH 4rwDMA Grant Trigger Enable, High Priority
0
B
FPI Bus transactions on RPB with low-priority
DMA channels as bus master are enabled for
grant trigger event generation.
1
B
FPI Bus transactions on RPB with low-priority
DMA channels as bus master are disabled for
grant trigger event generation.
DMAL 6rwDMA Grant Trigger Enable, Low Priority
0
B
FPI Bus transactions on RPB with high-priority
DMA channels as bus master are enabled for
grant trigger event generation.
1
B
FPI Bus transactions on RPB with high-priority
DMA channels as bus master are disabled for
grant trigger event generation.
0 [31:16] r Reserved
Read as 0; should be written with 0.