TC1796
System Units (Vol. 1 of 2)
CPU Subsystem
User’s Manual 2-12 V2.0, 2007-07
CPU, V2.0
In the TC1796, the MMU_CON register indicates the non-availability of the TriCore 1’s
memory management unit (bit MXT is always set).
MMU_CON
MMU Configuration Register (F7E18000
H
) Reset Value: 0000 8000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
NO
MMU
0 TSZ SZB SZA V
r r r rw rw rw
Field Bits Type Description
NOMMU 15 r No MMU Available
0
B
MMU is available
1
B
MMU is not available. All other bits of
MMU_CON are undefined.
0 [14:0],
[31:16]
r Reserved
Read as 0; should be written with 0.
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