TC1796
Peripheral Units (Vol. 2 of 2)
Synchronous Serial Interface (SSC)
User’s Manual 20-17 V2.0, 2007-07
SSC, V2.1
If the RXFIFO is flushed in Transparent Mode, the software must take care that a
previously pending receive interrupt becomes ignored.
Note: The RXFIFO Interrupt Trigger Level bit field RXFCON.RXFITL is “don’t care” in
Transparent Mode.
Transmit Operation
Interrupt generation for the TXFIFO depends on the TXFIFO filling level and the
execution of write operations to the register TB. Transparent Mode for the TXFIFO is
enabled when bits TXFCON.TXTMEN and TXFCON.TXFEN are set.
TIR is also activated after a TXFIFO flush operation or when the TXFIFO becomes
enabled (TXFCON.TXTMEN and TXFCON.TXFEN set) when it was previously disabled.
In these cases, the TXFIFO is empty and ready to be filled with data.
If the TXFIFO is full (FSTAT.TXFFL = 1000
B
) and an additional message is written into
the TB, a transmit interrupt will be generated after the TB write operation. In this case,
the data byte last written into the TXFIFO is overwritten and a TIR will be generated with
bit CON.TE set.
Note: The TXFIFO Interrupt Trigger Level bit field TXFCON.TXFITL is “don’t care” in
Transparent Mode.
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