TC1796
Peripheral Units (Vol. 2 of 2)
Micro Second Channel (MSC)
User’s Manual 21-4 V2.0, 2007-07
MSC, V2.0
Clock control, address decoding, and interrupt service request control are managed
outside the MSC module kernel. Service request outputs are able to trigger an interrupt
or a DMA request.
Features
• Fast synchronous serial interface to connect power switches in particular, or other
peripheral devices via serial buses
• High-speed synchronous serial transmission on downstream channel
– Serial output clock frequency: f
FCL
= f
MSC
/2
– Fractional clock divider for precise frequency control of serial clock f
MSC
– Command, data, and passive frame types
– Start of serial frame: Software-controlled, timer-controlled, or free-running
– Programmable upstream data frame length (16 or 12 bits)
– Transmission with or without SEL bit
– Flexible chip select generation indicates status during serial frame transmission
– Emergency stop without CPU intervention
• Low-speed asynchronous serial reception on upstream channel
– Baud rate: f
MSC
divided by 4, 8, 16, 32, 64, 128, or 256
– Standard asynchronous serial frames
– Parity error checker
– 8-to-1 input multiplexer for SDI lines
– Built-in spike filter on SDI lines
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