TC1796
Peripheral Units (Vol. 2 of 2)
Controller Area Network (MultiCAN) Controller
User’s Manual 22-85 V2.0, 2007-07
MultiCAN, V2.0
DIV8 15 rw Divide Prescaler Clock by 8
0
B
A time quantum lasts (BRP+1) clock cycles.
1
B
A time quantum lasts 8 × (BRP+1) clock cycles.
FTX 16 rw Fast Transmit (TTC only)
When a message is requested for transmission on the
CAN bus, then the SOF is sent with the beginning of
a new bit time.
If the CAN bus is in the idle state and bit FTX is set
(FTX = 1), a new bit time is started immediately with
the transmit trigger of a new message. This eliminates
the variable delay between the transmit trigger of a
message and the actual SOF signal on the transmit
output. Such a variable delay occurs when transmit
triggers occur at different positions within a CAN bit
time.
0 [31:17] r Reserved
Read as 0; should be written with 0.
Field Bits Type Description
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