Infineon Technologies TC1796 - Page 1387

TC1796
Peripheral Units (Vol. 2 of 2)
Controller Area Network (MultiCAN) Controller
User’s Manual 22-92 V2.0, 2007-07
MultiCAN, V2.0
RESNEWDAT,
SETNEWDAT
3,
19
w Reset/Set New Data
These bits control the clear/set condition for
NEWDAT (see Table 22-20).
RESMSGLST,
SETMSGLST
4,
20
w Reset/Set Message Lost
These bits control the clear/set condition for
MSGLST (see Table 22-20).
RESMSGVAL,
SETMSGVAL
5,
21
w Reset/Set Message Valid
These bits control the clear/set condition for
MSGVAL (see Table 22-20).
RESRTSEL,
SETRTSEL
6,
22
w Reset/Set Receive/Transmit Selected
These bits control the clear/set condition for RTSEL
(see Table 22-20).
RESRXEN,
SETRXEN
7,
23
w Reset/Set Receive Enable
These bits control the clear/sett condition for RXEN
(see Table 22-20).
RESTXRQ,
SETTXRQ
8,
24
w Reset/Set Transmit Request
These bits control the clear/set condition for TXRQ
(see Table 22-20).
RESTXEN0,
SETTXEN0
9,
25
w Reset/Set Transmit Enable 0
These bits control the clear/set condition for TXEN0
(see Table 22-20).
RESTXEN1,
SETTXEN1
10,
26
w Reset/Set Transmit Enable 1
These bits control the clear/set condition for TXEN1
(see Table 22-20).
RESDIR,
SETDIR
11,
27
w Reset/Set Message Direction
These bits control the clear/set condition for DIR
(see Table 22-20).
0 [15:12],
[31:28]
w Reserved
Should be written with 0.
Field Bits Type Description