TC1796
Peripheral Units (Vol. 2 of 2)
Controller Area Network (MultiCAN) Controller
User’s Manual 22-204 V2.0, 2007-07
MultiCAN, V2.0
Note: Additional details on the fractional divider register functionality are described in
section “Fractional Divider Operation” on Page 3-29 of the TC1796 User’s
Manual System Units part (Volume 1).
DISCLK 31 rwh Disable Clock
Hardware controlled disable for f
OUT
signal.
0 10,
[27:26]
rw Reserved
Read as 0; should be written with 0.
Field Bits Type Description
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