EasyManuals Logo

Infineon Technologies TC1796 User Manual

Infineon Technologies TC1796
2150 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #1538 background imageLoading...
Page #1538 background image
TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual 23-29 V2.0, 2007-07
MLI, V2.0
Transmitting Controller
In the transmitting controller, a write operation to a location within a Transfer Window
delivers the address, the data, and the data size to the transmitter and triggers the
following actions in the MLI transmitter.
The 16 least significant address bits of the Transfer Window write access are stored
in TPxAOFR.AOFF as write offset address. In case of a an access to a Small
Transfer Window, also 16 bits are stored, but the higher bits are not taken into
account.
The data of the write access to the Transfer Window is stored in TPxDATAR.DATA.
The data width of the write access to the Transfer Window (8-bit, 16-bit, or 32-bit) is
stored in bit field TPxSTATR.DW.
Status flag TRSTATR.DVx (data valid) is set, indicating that the pipe contains valid
data for transmission.
If the address prediction method is disabled (TCR.NO = 1), the transmission of a
Write Offset and Data Frame is started as soon as the MLI transmitter is idle, no
higher priority frames are pending, and TREADY = 1.
If the address prediction method is enabled (TCR.NO = 0), a Write Offset and Data
Frame is started only if an address prediction is not possible (indicated by
TPxSTATR.OP = 0). If TPxSTATR.OP = 1, an address prediction is possible in the
MLI transmitter (and the MLI receiver) and an Optimized Write Frame can be started.
The address prediction method used is described on Page 23-45.
Status flag TRSTATR.DVx is cleared by hardware and MLI event status flag
TISR.NFSIx (Normal Frame Sent event in pipe x) is set (and a service request output
is activated if enabled by TIER.NFSIEx = 1) after the Write Frame has been finished
and correctly acknowledged by the MLI receiver.
The number m of offset address bits that are transmitted at a Write Offset and Data
Frame is determined by the size of the Remote Window in the receiving controller that
has been previously initialized by the transmission of a Copy Base Address Frame.
Parameter m is referring to bit field TPxSTATR.BS (and RPxSTATR.BS) and can be in
the range of 1 to 16 bits.

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Infineon Technologies TC1796 and is the answer not in the manual?

Infineon Technologies TC1796 Specifications

General IconGeneral
BrandInfineon Technologies
ModelTC1796
CategoryController
LanguageEnglish