TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual 23-79 V2.0, 2007-07
MLI, V2.0
The fractional divider register allows the programmer to control the clock rate and period
of the module clocks f
MLI0
and f
MLI0
. The period of f
MLIx
can be either 1/STEP or a fraction
of STEP/1024 (for any value of STEP from 0 to 1023) of clock f
MLI
. Each MLI has its own
fractional divider.
FDR
Fractional Divider Register (0C
H
) Reset Value: 03FF 43FF
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIS
CLK
EN
HW
SUS
REQ
SUS
ACK
0RESULT
rwh rw rh rh r rh
1514131211109876543210
DM SC SM 0 STEP
rw rw rw r rw
Field Bits Type Description
STEP [9:0] rw Step Value
Reload or addition value for RESULT.
SM 11 rw Suspend Mode
SM selects between granted or immediate suspend
mode.
SC [13:12] rw Suspend Control
This bit field determines the behavior of the fractional
divider in suspend mode.
DM [15:14] rw Divider Mode
This bit field selects normal divider mode or fractional
divider mode.
RESULT [25:16] rh Result Value
Bit fields for the addition result.
SUSACK 28 rh Suspend Mode Acknowledge
Indicates the state of the SPNDACK signal.
SUSREQ 29 rh Suspend Mode Request
Indicates the state of the SPND signal.
ENHW 30 rw Enable Hardware Clock Control
Controls operation of ECEN input and DISCLK bit.
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