TC1796
System Units (Vol. 1 of 2)
Clock System and Control
User’s Manual 3-11 V2.0, 2007-07
Clock, V2.0
PLL Mode
In PLL Mode, the PLL is running. The VCO clock f
VCO
is derived from f
OSC
, divided by the
P factor, multiplied by the PLL (N-Divider). This mode is selected by setting
PLL_CLC.VCOBYP = 0. Further, f
CPU
and f
SYS
are derived from f
VCO
by the K-Divider.
The system clock f
SYS
can be equal to f
CPU
(PLL_CLC.SYSFS = 1) or equal to f
CPU
/2
(PLL_CLC.SYSFS = 0).
(3.2)
PLL Base Mode
In PLL Base Mode, the PLL is running at its VCO base frequency and f
CPU
and f
SYS
are
derived from f
VCO
only by the K-Divider. In this mode, PLL_CLC.VCOBYP must be 0 and
pin BYPASS must have been latched as 0 at the end of the last power-on reset
operation. In this mode, the system clock f
SYS
can be equal to f
CPU
(PLL_CLC.SYSFS = 1) or equal to f
CPU
/2 (PLL_CLC.SYSFS = 0).
(3.3)
f
SYS
= f
CPU
or f
CPU
/2
f
CPU
N
PK×
--------------
f
OSC
×=
f
SYS
= f
CPU
or f
CPU
/2
f
CPU
1
K
----
f
VCObase
×=
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