TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-14 V2.0, 2007-07
GPTA, V2.0
Figure 24-7 FPC Delayed Debounce Filter Algorithm with Timer Reset
The total signal delay from input to output depends on the programmed compare register
value, the number of high-frequency pulses (glitches) during the filter operating time, and
the timer behavior in case of a glitch (decrement or reset).
The FPC Delayed Debounce Filter Mode is selected by:
• FPCCTRk.MOD = 000
B
MCT05916
Total Signal Delay
Timer Threshold
must be cleared
by software
Signal Input
SIN
Timer Value
FPCCTRk.TIM
Level Output
SOLk
FPCSTAT.FEGk
FPCSTAT.REGk
Trigger Output
SOTk
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