TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-81 V2.0, 2007-07
GPTA, V2.0
When the comparator output signal changes from 1 to 0,
• the service request flag LTC63 is set,
• an interrupt request will be activated if enabled by bit field LTCCTR63.REN,
• the event output line EO is set to high level for one
f
GPTA
clock cycle.
As well as the16-bit compare register LTCXR63.X, the LTC63 also contains a 16-bit
shadow register LTCXR63.XS. Both 16-bit registers are combined in the 32-bit register
LTCXR. On an LTC input signal selected via the LTC input multiplexer, the contents of
the shadow register are copied to the compare register.
Standard PWM Mode
The LTC63 can be used for standard PWM duty cycle generation with enhanced update
features. For this purpose, a pair of LTCs with lower index is configured as reset
timer/period compare register. The user must set the period compare register to the
desired period - 2 and LTC63 to the desired duty cycle. With LTCCTR63.BRM = 0 (Bit
Reversal Mode), timer bit reversal is disabled. LTC63 is used for standard PWM Mode
but with enhanced update features due to the “greater” comparator. The compare
register LTCXR63.X can be written on-the-fly. If the duty cycle is changed at an arbitrary
time, the actual duty cycle for the current period will reflect the old duty cycle, the new
one, or a mixture of both. A duty cycle of 100% will be generated if the compare register
is set to FFFF
H
.
Pulse Count Modulation Mode (PCM)
With a period of 100 clocks and a duty cycle of 64%, standard PWM will produce an
output signal that is ON for 64 clock cycles and OFF for the remaining 36 clock cycles.
In contrast, pulse count modulation will generate 64 ON pulses and 36 OFF pulses
distributed over the whole period as evenly as possible. PCM offers higher output
frequency than standard PWM. This allows faster settling time e.g. when building a D/A
converter in conjunction with an external low-pass filter. Only for very short or very long
duty cycles does the method show no advantage or just little advantage compared to
standard PWM.
As with standard PWM, a pair of LTCs with lower index is configured as reset
timer/period compare register and LTC63 is used as duty cycle compare register. But
now, Bit BRM (Bit Reversal Mode) in the LTCCTR63 register is set to 1 which enables
the timer bit reversal to activate PCM.
The algorithm will also work if fewer than 16 timer bits are effectively used, even if the
period is not a power of two. In any case, the user must write the duty cycle in unsigned
16-bit fractional format to the compare register.
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