TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-108 V2.0, 2007-07
GPTA, V2.0
Figure 24-70 LTC Input Multiplexer Group (Programmer’s View)
The 1. level multiplexer is built up by five 8:1 multiplexers that are controlled in parallel
by bit field LIMLn. Bit field LIMGn controls the 2. level multiplexer and connects one of
the 1. level multiplexer outputs to one of the LIMGng outputs. The output of the 2. level
multiplexer is connected only to the input of an LTC if bit LIMENn is set (enable
multiplexer connection), and bit MRACTL.AEN is set (multiplexer array enabled), and no
reserved bit combination of LIMGn is selected. If one of these conditions is not true, the
corresponding LTC input will be held at a low level.
Two LTC Input Multiplexer Control Registers, LIMCRL and LIMCRH (see also
Page 24-202), are assigned to each of the LTC groups. Therefore, a total of sixteen
registers control the connections within the LTC input multiplexer of the GPTA module.
The LIMCRL registers control the LIMG output lines 0 to 3 and the GIMCRH registers
control the LIMG output lines 4 to 7. Table 24-12 lists all LTC Input Multiplexer Control
Registers with its control functions. Please note that all LTC Input Multiplexer Control
Registers are not directly accessible but must be written or read using a FIFO array
structure as described on Page 24-110.
MCA05979
MUX
8
I/O Group
(LIMG0g)
MUXMUX
I/O Group
(LIMG1g)
GTC Group
(LIMG2g)
2. Level
Mux
1. Level
Mux
3
MUX
Clock Group
(LIMG3g)
MUX
PDL/INT
Group
(LIMG4g)
MUX
LIMCRLg
LIMCRHg
(g = 0-7)
To Input n of
LTC Group g
LIMENn
0
MUX
0
1
MAEN
MRACTL
Registers
LIMGn
LIMLn
&
Not a reserved
LIMGn bit combination
3
8
8
8
8
010
001
000
011
100
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