TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-162 V2.0, 2007-07
GPTA, V2.0
RCK 4rwOutput Pulse on Rising Edge
0
B
DCM output line is not affected
1
B
DCM output line is provided with a single clock
pulse generated on a rising input signal edge
FCK 5rwOutput Pulse on Falling Edge
0
B
DCM output line is not affected
1
B
DCM output line is provided with a single clock
pulse generated on a falling input signal edge
QCK 6wAdditional Output Pulse Generation
0
B
DCM output line is not affected
1
B
DCM output line is immediately provided with a
single clock pulse
QCK is always read as 0.
RRE 7rwInterrupt Request on Rising Edge
0
B
Interrupt request is not affected
1
B
Interrupt request is set on rising input signal
edge
FRE 8rwInterrupt Request on Falling Edge
0
B
Interrupt request is not affected
1
B
Interrupt request is set on falling input signal
edge
CRE 9rwInterrupt Request on Compare Event
0
B
Interrupt request is not affected
1
B
Interrupt request is set when the timer matches
capture/compare register DCMCOVk
0 [31:10] r Reserved
Read as 0; should be written with 0.
Field Bits Type Description
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