TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-198 V2.0, 2007-07
GPTA, V2.0
GTC Input Multiplexer Control Registers
Two registers, GIMCRL and GIMCRH, are assigned to each GTCG[3:0]. GIMCRL
controls the connections of cells 0 to 3 in a GTC Group. GIMCRH controls the
connections of cells 4 to 7 in a GTC Group.
Note: These registers are not directly accessible and can be written and read only via
the multiplexer register array FIFO (see Section 24.2.4.5).
GIMCRLg (g = 0-3)
Input Multiplexer Control Register for Lower Half of GTC Group g
Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GIM
EN3
GIMG3 0 GIML3
GIM
EN2
GIMG2 0 GIML2
rrwrrwrrwrrw
1514131211109876543210
GIM
EN1
GIMG1 0 GIML1
GIM
EN0
GIMG0 0 GIML0
rw rw r rw rw rw r rw
Field Bits Type Description
GIML0,
GIML1,
GIML2,
GIML3
[2:0],
[10:8],
[18:16],
[26:24]
rw Multiplexer Line Selection
This bit field selects the input line of a GIMG that
can be selected by bit field GIMGn for GIMG
output n.
000
B
LIMG input IN0 selected
001
B
LIMG input IN1 selected
010
B
LIMG input IN2 selected
011
B
LIMG input IN3 selected
100
B
LIMG input IN4 selected
101
B
LIMG input IN5 selected
110
B
LIMG input IN6 selected
111
B
LIMG input IN7 selected
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