TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-266 V2.0, 2007-07
GPTA, V2.0
Note: Registers GPTA0_CLC, GPTA0_FDR, GPTA0_EDCTR and GPTA0_DBGCTR
are located in the address space of GPTA0.
The module clock f
CLC
is used inside the GPTA module kernels for control purposes such
as clocking of control logic and register operations. The frequency of f
CLC
is identical to
the system clock frequency f
SYS
. The clock control registers GPTA0_CLC make it
possible to enable/disable f
CLC
under certain conditions.
The three separate module timer clocks
f
GPTA0
, f
GPTA1
, and f
LTCA2
are used inside the
GPTA module kernels as input clocks for the timers. All three module timer clocks have
the same frequency as
f
GPTA
(as selected through register GPTA0_FDR) and can be
enabled/disabled separately each through register GPTA0_ECDTR.
Attention: If f
GPTA0
, f
GPTA1
, and f
LTCA2
are disabled by the enable bits in register
GPTA0_ECDTR, f
CLC
keeps on running. In this case, that means that
register accesses to the GPTA modules are possible.
The frequency of f
GPTA
is defined by:
(24.6)
(24.7)
Note: The upper formula applies to normal divider mode of the fractional divider
(GPTA0_FDR.DM = 01
B
). The lower formula applies to fractional divider mode
(GPTA0_FDR.DM = 10
B
).
The debug clock control register additionally makes it possible to control the timer clocks
f
GPTA0
, f
GPTA1
, and f
LTCA2
for debug purposes on basis of a clock counter.
If the debug clock feature is enabled (GPTA0_DBGCTR.DBGCEN = 1) and bit
GPTA0_DBGCTR.DBGCST is set, the timer clocks f
GPTA0
, f
GPTA1
, and f
LTCA2
will be
activated in parallel for as many clock cycles as have been programmed into bit field
GPTA0_DBGCTR.CLKCNT. When the debug clock feature becomes enabled, bit field
CLKCNT counts down and stops counting at 0000
H
. Bit DBGCST is again cleared by
hardware after the programmed number of clock pulses has been issued. This feature
makes it possible to single step the GPTA modules with a programmable timer clock
granularity.
Attention: If the frequencies of the module timer clocks f
GPTA0
, f
GPTA1
, or f
LTCA2
are
configured to be smaller than the control clock f
CLC
(as programmed in
register GPTA0_FDR) or even disabled (as programmed in register
GPTA0_EDCTR), an action initiated by a write access to a module
register could be significantly delayed, because the register write
access is clocked by f
CLC
and the register content is evaluated by
hardware using the slower or disabled module timer clocks f
GPTA0
,
f
GPTA1
, or f
LTCA2
.
f
GPTA
f
SYS
1
n
---
× with n = 1024 - FDR.STEP or =
f
GPTA
f
SYS
n
1024
-------------
× with n = 0-1023 =
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