TC1796
Peripheral Units (Vol. 2 of 2)
Analog-to-Digital Converter (ADC)
User’s Manual 25-27 V2.0, 2007-07
ADC, V2.0
generated for the control information of register QUEUE0, if the queue is enabled (bit
CON.QEN = 1), the queue status register contains valid data (QUEUE0.V is set) and the
queue gating line QGT = 1. The arbitration participation flag is automatically cleared if all
queue elements, the queue status register (remember: QUEUE0 represents the
contents of queue element number zero) and the back-up register contain no valid
request.
Figure 25-15 Conversion Request Source “Queue”
If a currently running conversion initiated by “Queue” is cancelled, the arbiter restores
the conversion information in the back-up for this channel. In this context, conversion
information refers to the conversion request bit, the setting for the external multiplexer
and the settings of the A/D Converter’s resolution. If the back-up register contains valid
conversion information, the arbiter reads from the back-up register instead of the queue
status register. Thus, the previously cancelled conversion participates in arbitration once
again. A conversion requested via the queue storage block (register QUEUE0) will be
performed after the request in the back-up register is served.
The valid bit (V bit) of the queue status register and the back-up register can be
cancelled under software control. Clearing the queue arbitration participation bit clears
either the valid bit in the queue status register (if the back-up register contains no
request) or the request bit in the back-up register (if the back-up register contains a valid
request). If the valid bit of the queue status register is cleared, a slide operation is
MCA06018
Clear REQ
on reset
by software
V GRPS EMUX RES CHNR
Back-up Register
V GRPS EMUX RES CHNR
QUEUE0
Set/Reset
by Arbiter
Reset
by Arbiter
AP.QP
Reset by Software
&
Queue Gating
Input QGT
Set
QEN
≥1
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