Infineon Technologies TC1796 User Manual

TC1796
System Units (Vol. 1 of 2)
System Control Unit
User’s Manual 5-21 V2.0, 2007-07
SCU, V2.0
LDEN2 10 rw Level Detection Enable 2
This bit determines if bit INTF2 is cleared
automatically if an edge of the input signal IN2 is
detected, which has not been selected (rising edge
with REN2 = 0 or falling edge with FEN2 = 0).
0
B
Bit INTF2 will not be cleared.
1
B
Bit INTF2 will be cleared.
EIEN2 11 rw External Interrupt Enable 2
This bit enables the generation of a trigger event for
request channel 2 (e.g. for interrupt generation) when
a selected edge is detected.
0
B
The trigger event is disabled.
1
B
The trigger event is enabled.
INP2 [14:12] rw Interrupt Node Pointer
This bit field determines the destination (output
channel) for trigger event 2 (if enabled by EIEN2).
X00
B
The event of input channel 2 triggers output
channel 0 (signal INT20).
X01
B
The event of input channel 2 triggers output
channel 1 (signal INT21).
X10
B
The event of input channel 2 triggers output
channel 2 (signal INT22).
X11
B
The event of input channel 2 triggers output
channel 3 (signal INT23).
EXIS3 [21:20] rw External Input Selection 3
This bit field determines which input line is selected
for signal IN3.
00
B
Input IN30 is selected.
01
B
Input IN31 is selected.
10
B
Input IN32 is selected.
11
B
Input IN33 is selected.
FEN3 24 rw Falling Edge Enable 3
This bit determines if the falling edge of signal IN3 is
used to set bit INTF3.
0
B
The falling edge is not used.
1
B
The detection of a falling edge of IN3 generates
a trigger event (INTF3 becomes set).
Field Bits Type Description

Infineon Technologies TC1796 Specifications

General

Brand	Infineon Technologies
Model	TC1796
Category	Controller
Language	English