TC1796
System Units (Vol. 1 of 2)
Program Memory Unit
User’s Manual 7-5 V2.0, 2007-07
PMU, V2.0
The PFLASH array delivers 256-bit wide read data with one read access. In the TC1796,
these 256 bits are transferred to the CPU and PMI via the 64-bit wide Program Local
Memory Bus (PLMB) using single-cycle burst transfers with four 64-bit transfers. During
such a burst transfer, the next sequential 256-bit read data is prefetched from the
PFLASH. Therefore, except a delay of the first initial read data access, sequential burst
transfers are provided, supporting the highest possible instruction throughput from
PFLASH to the CPU with execution of two 32-bit instructions in one cycle. Also non-
cached instruction accesses are burst accesses with up to four double-word transfers.
Each PFLASH sector can be separately locked against erasing and reprogramming.
Write operations to a locked and protected sector are only possible only if the sector is
temporarily unlocked using a dedicated password check sequence. Additionally, also an
OTP (One Time Programmable) function can be selected for each sector. An OTP sector
is locked forever, and erasing and reprogramming is no longer possible.
Features of Program Flash
• 2 Mbyte on-chip program Flash memory
• Usable for instruction code execution or constant data storage
• 256-byte wide program interface
– 256 bytes are programmed into PFLASH page in one step/command
• 256-bit read interface
– Transfer from PFLASH to CPU/PMI by four 64-bit single-cycle burst transfers
• Dynamic correction of single-bit errors during read access
• Detection of double bit errors
• Fixed sector architecture
– Eight 16 Kbyte, one 128 Kbyte, one 256 Kbyte, and three 512 Kbyte sectors
– Each sector separately erasable
– Each sector separately write-protectable
• Configurable read protection for complete PFLASH with sophisticated read access
supervision, combined with write protection for complete PFLASH (protection against
“Trojan horse” software)
• Configurable write protection for each sector
– Each sector separately write-protectable
– With capability to be re-programmed
– With capability to be locked forever (OTP)
• Password mechanism for temporarily disable write or read protection
• On-chip programming voltage generation
• PFLASH is delivered in erased state (read all zeros)
• JEDEC standard based command sequences for PFLASH control
– Write state machine controls programming and erase operations
– Status and error reporting by status flags and interrupt
• Margin check for detection of problematic PFLASH bits
To Next Page
Loading...
Need help?
General