TC1796
System Units (Vol. 1 of 2)
Program Memory Unit
User’s Manual 7-8 V2.0, 2007-07
PMU, V2.0
Features of Data Flash
• 128 Kbyte on-chip data Flash memory, organized in two 64 Kbyte banks
• Usable for data storage with EEPROM functionality
• 128 byte program interface
– 128 bytes are programmed into one DFLASH page by one step/command
• 64-bit read interface (no burst transfers)
• Dynamic correction of single-bit errors during read access
• Detection of double bit errors
• Fixed sector architecture
– Two 64 Kbyte banks/sectors
– Each sector separately erasable
• Configurable read protection (combined with write protection) for complete DFLASH
together with PFLASH read protection
• Password mechanism to temporarily disable write and read protection
• Erasing/programming of one bank possible while reading data from the other bank
• Programming of one bank possible while erasing the other bank
• On-chip generation of programming voltage
• DFLASH is delivered in erased state (read all zeros)
• JEDEC-standard based command sequences for DFLASH control
– Write state machine controls programming and erase operations
– Status and error reporting by status flags and interrupt
• Margin check for detection of problematic DFLASH bits
The DFLASH contains two 64 Kbyte sectors, DS0 and DS1, which are identical with
banks DB0 and DB1. DFLASH pages are always 128-byte wide.
Table 7-2 DFLASH Bank and Page Definitions
Numbering Size Cached
Address Range
Non-Cached
Address Range
DFLASH Sectors (and Banks)
DS0 (= DB0) 64 Kbyte 8FE0 0000
H
- 8FE0 FFFF
H
AFE0 0000
H
- AFE0 FFFF
H
DS1 (= DB1) 64 Kbyte 8FE1 0000
H
- 8FE1 FFFF
H
AFE1 0000
H
- AFE1 FFFF
H
DFLASH Pages
DS0 DP0 128 byte 8FE0 0000
H
- 8FE0 007F
H
AFE0 0000
H
- AFE0 007F
H
DPn
1)
128 byte (8FE0 0000
H
+ OFF) -
(8FE0 0000
H
+ OFF + 7F
H
)
(with OFF = n × 80
H
)
(AFE0 0000
H
+ OFF) -
(AFE0 0000
H
+ OFF + 7F
H
)
(with OFF = n × 80
H
)
DP511 128 byte 8FE0 FF80
H
- 8FE0 FFFF
H
AFE0 FF80
H
- AFE0 FFFF
H
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