Infineon Technologies TC1796 - Page 45

TC1796
System Units (Vol. 1 of 2)
Introduction
User’s Manual 1-6 V2.0, 2007-07
Intro, V2.0
FPU Floating Point Unit
GPIO General Purpose Input/Output
GPR General Purpose Register
GPTA General Purpose Timer Array
ICACHE Instruction Cache
I/O Input / Output
LDRAM Local Data RAM
LFI Local Memory-to-FPI Bus Interface
LMB Local Memory Bus
LMI Local Memory Interface
LSB Least Significant Bit
LTCA Local Timer Cell Array
MLI Micro Link Interface
MMU Memory Management Unit
MSB Most Significant Bit
MSC Micro Second Channel
NMI Non-Maskable Interrupt
OCDS On-Chip Debug Support
OVRAM Code Overlay Memory
PBCU Program Local Memory Bus Control Unit
PCP Peripheral Control Processor
PFLASH Program Flash Memory
PMI Program Memory Interface
PMU Program Memory Unit
PLL Phase Locked Loop
PLMB Program Local Memory Bus
PMU Program Memory Unit
PRAM PCP Parameter RAM
RAM Random Access Memory
RBCU Remote Peripheral Bus Control Unit
RISC Reduced Instruction Set Computing
RPB Remote Peripheral Bus