Infineon Technologies TC1796 User Manual

TC1796
System Units (Vol. 1 of 2)
Memory Maps
User’s Manual 9-21 V2.0, 2007-07
MemMaps, V2.0
13
3)
D000 0000
H
-
D000 DFFF
H
56
Kbyte
DMI Local Data RAM
(LDRAM)
ignore ignore
D000 E000
H
-
D000 FFFF
H
8 Kbyte DMI Dual-Port RAM
(DPRAM)
D001 0000
H
-
D3FF FFFF
H
≈ 64
Mbyte
Reserved Trap Trap
D400 0000
H
-
D400 BFFF
H
48
Kbyte
Reserved
(PMI Scratch-Pad RAM)
ignore ignore
4)
D400 C000
H
-
D7FF FFFF
H
≈ 64
Mbyte
Reserved PLMBBET &
DLMBBET
PLMBBE
D800 0000
H
-
DDFF FFFF
H
96
Mbyte
External Peripheral Space EBU
access
EBU
access
DE00 0000
H
-
DEFF FFFF
H
16
Mbyte
External Emulator Space EBU
access
EBU
access
DF00 0000
H
-
DFFF BFFF
H
≈ 16
Mbyte
Reserved DLMBBET &
SPEBET
SPEBE
DFFF C000
H
-
DFFF DFFF
H
8 Kbyte Boot ROM (BROM)
DFFF E000
H
-
DFFF FFFF
H
8 Kbyte Test ROM (TROM)
14
3)
E000 0000
H
-
E7FF FFFF
H
128
Mbyte
External Peripheral Space EBU
access
EBU
access
E800 0000
H
-
EFFF FFFF
H
128
Mbyte
Reserved DLMBBE DLMBBE
15
3)
F000 0000
H
-
FFFF FFFF
H
256
Mbyte
Address map is identical to FPI Bus segment 15
address map (see Table 9-3).
1) Cached area
2) Only applicable when writing Flash command sequences
3) Non-cached area
4) In case of a byte access, a PLMBBET is generated
Table 9-5 DLMB Address Map (cont’d)
Seg-
ment
Addresses Size Description Action
Read Write

Infineon Technologies TC1796 Specifications

General

Brand	Infineon Technologies
Model	TC1796
Category	Controller
Language	English