TC1796
System Units (Vol. 1 of 2)
Introduction
User’s Manual 1-11 V2.0, 2007-07
Intro, V2.0
– 16 Kbyte Instruction Cache (ICACHE)
– 16 Kbyte Boot ROM (BROM)
• Data memory
– 64 Kbyte Data Memory (SRAM)
– 16 Kbyte data memory (SBRAM) for standby operation during power-down
– 56 Kbyte Local Data RAM (LDRAM)
– 8 Kbyte Dual-port RAM (DPRAM)
– 128 Kbyte on-chip Data Flash (DFLASH)
•PCP
– 32 Kbyte PCP Code Memory (CMEM)
– 16 Kbyte PCP Data Memory (PRAM)
• On-chip SRAMs with parity error detection
Interrupt System
• Total of 181 Service Request Nodes (SRNs)
• Flexible interrupt-prioritizing scheme with 255 interrupt priority levels
• Fast interrupt response
• Service requests are serviced by CPU or PCP
Peripheral Control Processor (PCP)
• Data move between any two memory or I/O locations
• Data move until predefined limit reached supported
• Read-Modify-Write capabilities
• Full computation capabilities including basic MUL/DIV
• Read/move data and accumulate it to previously read data
• Read two data values and perform arithmetic or logical operation and store result
• Bit-handling capabilities (testing, setting, clearing)
• Flow-control instructions (conditional/unconditional jumps, breakpoint)
DMA Controller
• 16 independent DMA channels
• Programmable priority of the DMA sub-blocks on the bus interfaces
• Buffer capability for move actions on the buses (minimum of 1 move per bus is
buffered).
• Individually programmable operation modes for each DMA channel
• Full 32-bit addressing capability of each DMA channel
• Programmable data width of DMA transfer/transaction: 8-bit, 16-bit, or 32-bit
• Micro Link bus interface support
• One register set for each DMA channel
• Flexible interrupt generation
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