TC1796
System Units (Vol. 1 of 2)
Peripheral Control Processor (PCP)
User’s Manual 11-60 V2.0, 2007-07
PCP, V2.0
Note: An interrupt request with the SRPN held in PCP_CS.ESR is posted to the CPU
whenever a PCP error event, other than an FPI Bus error occurs. FPI Bus error
interrupt generation is automatically handled by the FPI Bus control logic, rather
than by the PCP. The execution of a DEBUG instruction is not classed as an error
event and does not therefore generate an interrupt request to the CPU. The entire
IAE 3rhInstruction Address Error
Set if the last error/debug event was an error
generated by the PCP attempting to fetch an
instruction from an address outside the implemented
CMEM range as a result of a jump or branch
instruction; otherwise, clear.
DBE 4rhDebug Event Flag
Set if the last error/debug event was a debug event.
Note: A debug event does not cause the posting of an
interrupt to the CPU.
0 5rReserved
Read as 0.
CWD 6rhChannel Watchdog Triggered
Set if the last error/debug event was an error
generated by a channel program attempting to
execute more instructions than allowed by
PCP_CS.CWT.
PPC 7rhPRAM Partitioning Check
Set if the last error/debug event was an error
generated by a channel program attempting to
perform a write to a PRAM address within the CSA, or
receipt of an interrupt request that would have caused
a context restore from outside the CSA.
EPN [15:8] rh Error Service Request Priority Number
Channel number of the channel that was operating
when the last error/debug event occurred. The value
stored is the SRPN which invoked this channel (=
channel number), NOT the current PCP priority
number stored in field CPPN in register PICR. Default
= 00
H
EPC [31:16] rh Error PC
PC value of the instruction that was executing when an
error or debug event occurred. Default = 0000
H
.
Field Bits Type Description
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