TC1796
System Units (Vol. 1 of 2)
Peripheral Control Processor (PCP)
User’s Manual 11-62 V2.0, 2007-07
PCP, V2.0
PARBCYC [25:24] rw Number of Arbitration Cycles Control
This bit field controls the number of arbitration cycles
used to determine the request with the highest priority.
It follows the same coding scheme as described for the
CPU interrupt arbitration.
00
B
Four arbitration cycles (default)
01
B
Three arbitration cycles
10
B
Two arbitration cycles
11
B
One arbitration cycle
PONECYC 26 rw Clocks per Arbitration Cycle Control
This bit determines the number of clocks per arbitration
cycle.
0
B
Two clocks per arbitration cycle (default)
1
B
One clock per arbitration cycle
0 [15:9],
[31:27]
r Reserved
Read as 0; should be written with 0.
Field Bits Type Description
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