TC1796
System Units (Vol. 1 of 2)
Peripheral Control Processor (PCP)
User’s Manual 11-65 V2.0, 2007-07
PCP, V2.0
IP1E 9rPCP Interrupt Bus 1 Enable
This bit reflects the status of interrupt bus 1 (PCP
interrupt arbitration bus). Interrupt bus 1 is always
enabled.
IP2E 10 r PCP Interrupt Bus 2 Enable
This bit reflects the status of interrupt bus 2. Interrupt
bus 2 is always disabled (not implemented in the
TC1796).
IP3E 11 r PCP Interrupt Bus 3 Enable
This bit reflects the status of interrupt bus 3. Interrupt
bus 3 is always disabled (not implemented in the
TC1796).
0 [31:12] r Reserved
Read as 0.
Field Bits Type Description
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