TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-7 V2.0, 2007-07
DMA, V2.0
the source or destination address register. In this case, no buffering of the address is
required. When writing a new address to the (address of) the source or destination
address register and a DMA transaction is running, no transfer to an address register can
take place and SHADRmn holds the new address value that was written. For this
operation, bit field ADRCRmn.SHCT must be set either to 01
B
(address is a source
address) or 10
B
(new address is a destination address). At the start of the next DMA
transaction, the shadow transfer takes place and the content of SHADRmn is written
either into SADRmn or DADRmn (ADRCRmn.SHCT must be set accordingly). After the
shadow transfer, SHADRmn is set to 0000 0000
H
. Therefore, the software can check by
reading the shadow address register whether or not the shadow transfer has already
taken place.
Only one address register can be shadowed while a transaction is running, because the
shadow register can only be assigned either to the source or to the destination address
register. Note that the shadow address register transfer has the same behavior in Single
or Continuous Mode. When the shadow mechanism is disabled
(ADRCRmn.SHCT = 00
B
), SHADRmn is always read as 0000 0000
H
.
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