TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-49 V2.0, 2007-07
DMA, V2.0
Note: This register is only reset by the OCDS reset.
SUSEN1x
(x = 0-7)
8+x rw Suspend Enable for DMA Channel 1x
This bit enables the soft suspend capability
individually for each DMA channel 1x.
0
B
DMA channel 1x is disabled for Soft-suspend
Mode. The DMA channel 1x does not react on
an active suspend request signal SUSREQ.
1
B
DMA channel 1x is enabled for Soft-suspend
Mode. If the suspend request signal SUSREQ
becomes active, a DMA transaction of DMA
channel 1x is stopped after the current DMA
transfer has been finished.
Soft-suspend Mode can be terminated when
SUSEN1x is written with 0.
SUSAC0x
(x = 0-7)
16+x rh Suspend Active for DMA Channel 0x
This status bit indicates whether DMA channel 0x is
in Soft-suspend Mode or not.
0
B
DMA channel 0x is not in Soft-suspend Mode
or internal actions are not yet finished after the
Soft-suspend Mode was requested.
1
B
DMA channel 0x is in Soft-suspend Mode.
SUSAC1x
(x = 0-7)
24+x rh Suspend Active for DMA Channel 1x
This status bit indicates whether DMA channel 1x is
in Soft-suspend Mode or not.
0
B
DMA channel 1x is not in Soft-suspend Mode
or internal actions are not yet finished after the
Soft-suspend Mode was requested.
1
B
DMA channel 1x is in Soft-suspend Mode.
Field Bits Type Description
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