TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-55 V2.0, 2007-07
DMA, V2.0
The bits in the Hardware Transaction Request Register enable or disable DMA hardware
requests.
DMA_HTREQ
DMA Hardware Transaction Request Register
(01C
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DCH
17
DCH
16
DCH
15
DCH
14
DCH
13
DCH
12
DCH
11
DCH
10
DCH
07
DCH
06
DCH
05
DCH
04
DCH
03
DCH
02
DCH
01
DCH
00
wwwwwwwwwwwwwwww
1514131211109876543210
ECH
17
ECH
16
ECH
15
ECH
14
ECH
13
ECH
12
ECH
11
ECH
10
ECH
07
ECH
06
ECH
05
ECH
04
ECH
03
ECH
02
ECH
01
ECH
00
wwwwwwwwwwwwwwww
Field Bits Type Description
ECH0x
(x = 0-7)
xwEnable Hardware Transfer Request
for DMA Channel 0x
ECH1x
(x = 0-7)
8+x w Enable Hardware Transfer Request
for DMA Channel 1x
DCH0x
(x = 0-7)
16+x w Disable Hardware Transfer Request
for DMA Channel 0x
DCH1x
(x = 0-7)
24+x w Disable Hardware Transfer Request
for DMA Channel 1x
Table 12-7 Conditions to Set/Clear the Bits TRSR.HTREmx
HTREQ.ECHmx HTREQ.DCHmx Transaction Finishes
1)
for Channel mx
1) In Single Mode only. In Continuous Mode, the end of a transaction has no impact.
Modification of
TRSR.HTREmx
0
B
0
B
0
B
Unchanged
1
B
0
B
0
B
Set
X
B
1
B
X
B
Clear
X
B
X
B
1
B
Clear
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