Infineon Technologies TC1796 - Page 721

TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-57 V2.0, 2007-07
DMA, V2.0
EME0DER 17 rw Enable Move Engine 0 Destination Error
This bit enables the generation of a Move Engine 0
destination error interrupt.
0
B
Move Engine 0 destination error interrupt is
disabled.
1
B
Move Engine 0 destination error interrupt is
enabled.
EME1SER 18 rw Enable Move Engine 1 Source Error
This bit enables the generation of a Move Engine 1
source error interrupt.
0
B
Move Engine 1 source error interrupt is disabled.
1
B
Move Engine 1 source error interrupt is enabled.
EME1DER 19 rw Enable Move Engine 0 Destination Error
This bit enables the generation of a Move Engine 0
destination error interrupt.
0
B
Move Engine 1 destination error interrupt is
disabled.
1
B
Move Engine 1 destination error interrupt is
enabled.
ME0INP [23:20] rw Move Engine 0 Error Interrupt Node Pointer
ME0INP determines the number n (n = 0-15) of the
service request output SRn that becomes active on a
Move Engine 0 source or destination interrupt.
0000
B
SR0 selected for Move Engine 0 interrupt
0001
B
SR1 selected for Move Engine 0 interrupt
…
B
…
1110
B
SR14 selected for Move Engine 0 interrupt
1111
B
SR15 selected for Move Engine 0 interrupt
Note: In the TC1796 only SR[7:0] are connected to
interrupt nodes.
Field Bits Type Description