Infineon Technologies TC1796 - Page 757

TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-93 V2.0, 2007-07
DMA, V2.0
03 CH02_OUT DMA channel 02 CHCR03.PRSEL = 000
B
SCU_REQ3 Ext. Request Unit
1)
CHCR03.PRSEL = 001
B
SR5 ADC0 CHCR03.PRSEL = 010
B
SR5 ADC1 CHCR03.PRSEL = 011
B
SR5 MLI0 CHCR03.PRSEL = 100
B
SR5 MLI1 CHCR03.PRSEL = 101
B
TIR SSC1 CHCR03.PRSEL = 110
B
not connected (0) CHCR03.PRSEL = 111
B
04 CH03_OUT DMA channel 03 CHCR04.PRSEL = 000
B
SCU_REQ0 Ext. Request Unit
1)
CHCR04.PRSEL = 001
B
TIR ASC0 CHCR04.PRSEL = 010
B
RIR ASC0 CHCR04.PRSEL = 011
B
TIR ASC1 CHCR04.PRSEL = 100
B
INT_O0 MultiCAN CHCR04.PRSEL = 101
B
TIR SSC0 CHCR04.PRSEL = 110
B
not connected (0) CHCR04.PRSEL = 111
B
05 CH04_OUT DMA channel 04 CHCR05.PRSEL = 000
B
SCU_REQ1 Ext. Request Unit
1)
CHCR05.PRSEL = 001
B
TIR ASC1 CHCR05.PRSEL = 010
B
RIR ASC1 CHCR05.PRSEL = 011
B
TIR ASC0 CHCR05.PRSEL = 100
B
INT_O0 MultiCAN CHCR05.PRSEL = 101
B
RIR SSC0 CHCR05.PRSEL = 110
B
not connected (0) CHCR05.PRSEL = 111
B
Table 12-9 DMA Request Assignment for DMA Sub-Block 0 (cont’d)
DMA
Channel
DMA Request Line DMA Requesting Unit Selected by