TC1796
System Units (Vol. 1 of 2)
LMB External Bus Unit
User’s Manual 13-42 V2.0, 2007-07
EBU, V2.0
• Asserts the MR/W signal according to the type of access to be performed (low in the
case of a write access, not used in burst read cycles). This level is retained until the
start of the next Address Phase.
• At the end of the Address Phase the EBU returns the ADV signal to high.
The length (number of LMBCLK cycles) of the Address Phase is programmed via the
EBU_BUSAPx.ADDRC bit field parameter. Additionally, the length of the Address Phase
selected via ADDRC can be multiplied by the EBU_BUSCONx.CMULT parameter, but
only if bit EBU_BUSCONx.MULTMAP[0] is set (ADDRC multiplier function enabled).
The calculation of the number of LMBCLK cycles in the Address Phase is described in
the following table:
The equivalent control capability is available for bit field EBU_EMUBAP.ADDRC, that
can be multiplied by EBU_EMUBCx.CMULT if bit EBU_EMUBC.MULTMAP[0] is set.
When an access is performed at a burst read cycle, the start of the Address Phase is
always synchronized to a rising edge of the appropriate BFCLK signal (BFCLK0 for
accesses to Type 0 devices and BFCLK1 for accesses to Type 1 devices). This allows
the programming of the EBU to correctly latch the data issued by the Burst Flash.
BFCLKO is used during a burst access to cause a Flash device to output the next
sequential data value.
MULTMAP Number of Address Phase Cycles
XXXXXX0
B
= ADDRC
XXXXXX1
B
= ADDRC × CMULT
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