TC1796
System Units (Vol. 1 of 2)
LMB External Bus Unit
User’s Manual 13-94 V2.0, 2007-07
EBU, V2.0
CMULT [15:13] rw Cycle Multiplier Control
This bit field specifies a multiplier for the cycles
specified via MULTMAP. WAITRDC, WAITWRC,
DTARDWR and DTACS always use this multiplier.
000
B
Multiplier is 1.
001
B
Multiplier is 4.
010
B
Multiplier is 8.
011
B
Multiplier is 16.
100
B
Multiplier is 32 (default after reset).
101
B
Reserved.
11X
B
Reserved.
ENDIAN 16 rw Endian Mode
0
B
Little-endian access mode selected
(default after reset).
1
B
Big-endian access mode selected.
DLOAD 17 rw Enforce Data Upload from External Bus
0
B
Data access is fed from data write buffer if it is
available (default after reset).
1
B
Data access is always fed from the external bus
access.
PREFETCH 18 rw Prefetch Mechanism for Each Code Access
0
B
Code access never uses prefetch buffer
mechanism (default after reset).
1
B
Code access always uses prefetch buffer
mechanism.
WAITINV 19 rw Reversed Polarity at WAIT
0
B
Input signal at the WAIT pin is active low
(default after reset).
1
B
Input signal at the WAIT pin is active high
(reversed polarity).
This bit has no effect when using Burst Flash Data
Handshake Mode.
Field Bits Type Description
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