Infineon Technologies TC1796 - Page 887

TC1796
System Units (Vol. 1 of 2)
LMB External Bus Unit
User’s Manual 13-109 V2.0, 2007-07
EBU, V2.0
WAITRDC [24:22] rw Read Command Phase Cycles
This bit field determines the basic number of
Command Phase clock cycles during read accesses.
The total number of Command Phase clock cycles for
read accesses is defined by WAITRDC multiplied by
EBU_EMUBC.CMULT (see also Page 13-43).
000
B
Reserved; do not use this combination.
001
B
1 clock cycle selected.
010
B
2 clock cycle selected.
…
B
…
111
B
7 clock cycle selected.
CMDDELAY [27:25] rw Command Delay Cycles
This bit field determines the basic number of
Command Delay phase clock cycles. The total
number of Command Delay phase clock cycles
further depends on bit fields EBU_EMUBC.CMULT
and EBU_EMUBC.MULTMAP[2] (see also
Page 13-43).
000
B
0 clock cycle selected.
001
B
1 clock cycle selected.
…
B
…
110
B
6 clock cycles selected.
111
B
7 clock cycles selected.
1 28 r Reserved
Reading these bits will return the value last written;
read as 1 after reset.
0 29 r Reserved
Reading these bits will return the value last written;
read as 0 after reset.
ADDRC [31:30] rw Address Cycles
This bit field determines the basic number of clock
cycles of the address phase. The total number of
address cycles further depends on bit fields
EBU_EMUBC.CMULT and
EBU_EMUBC.MULTMAP[0] (see also Page 13-41).
00
B
1 clock cycle selected
01
B
1 clock cycle selected
10
B
2 clock cycles selected
11
B
3 clock cycles selected
Field Bits Type Description