Infineon Technologies TC1796 - Page 920

TC1796
System Units (Vol. 1 of 2)
System Timer
User’s Manual 15-3 V2.0, 2007-07
STM, V2.0
Figure 15-1 General Block Diagram of the STM Module Registers
STM Module
00
H
STM_CAP
STM_TIM6
STM_TIM5
00
H
55 47 39 31 23 15 7
56-Bit System Timer
Address
Decoder
Clock
Control
Enable /
Disable
f
STM
MCB05746
31 23 15 7
Compare Register 0
Interrupt
Control
Compare Register1
STMIR1
STMIR0
PORST
0
0
31 23 15 7 0
STM_TIM4
STM_TIM3
STM_TIM2
STM_TIM1
STM_TIM0
STM_CMP1
STM_CMP0