TC1796
System Units (Vol. 1 of 2)
Watchdog Timer
User’s Manual 16-4 V2.0, 2007-07
WDT, V2.0
Table 16-1 TC1796 Registers Protected via the Endinit Feature
Registers Description
mod_CLC All clock control registers of the individual peripheral modules are
Endinit-protected.
mod_FDR All clock fractional divider registers of the individual peripheral
modules are Endinit-protected.
BTV, BIV, ISP Trap and interrupt vector table pointer as well as the interrupt stack
pointer are Endinit-protected.
WDT_CON1 The WDT Control Register 1, which controls the disabling and the
input frequency of the WDT, is Endinit-protected. In addition, its
bits will only have an effect on the WDT when ENDINIT is properly
set to 1 again.
RST_REQ
OSC_CON
PLL_CLC
SCU_SCLKFDR
SCU_EMSR
SCU_TCCON
SCU_CON
SCU_TCLR0
SCU_TCLR1
SCU_PTCON
Px_PDR
Px_ESR
PCP_CS
DMA_OCDSR
DMA_SUSPMR
FLASH_FCON
FLASH_MARP
DMI_CON
DMI_CON1
PMI_CON0
DMA_MEnAENR
DMA_MEnARR
MLIx_AER
MLIx_ARR
All these registers are also Endinit-protected.
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