TC1796
System Units (Vol. 1 of 2)
Register Overview
User’s Manual 18-9 V2.0, 2007-07
Regs, V2.0
EICR1 External Input Channel
Register 1
F000 0084
H
U, SV U, SV 0000 0000
H
EIFR External Input Flag
Register
F000 0088
H
U, SV U, SV 0000 0000
H
FMR Flag Modification Register F000 008C
H
U, SV U, SV 0000 0000
H
PDRR Pattern Detection Result
Register
F000 0090
H
U, SV U, SV 0000 000F
H
IGCR0 Interrupt Gating Register
0
F000 0094
H
U, SV U, SV 0000 0000
H
IGCR1 Interrupt Gating Register
1
F000 0098
H
U, SV U, SV 0000 0000
H
TGADC0 Trigger Gating ADC0
Register
F000 009C
H
U, SV U, SV 0000 0000
H
TGADC1 Trigger Gating ADC1
Register
F000 00A0
H
U, SV U, SV 0000 0000
H
– Reserved F000 00A4
H
BE BE –
– Reserved; these locations
should not be written.
F000 00A8
H
F000 00AC
H
–––
SCU_
PTCON
SCU Pad Test Control
Register
F000 00B0
H
U, SV SV, E 0000 0000
H
SCU_
PTDAT0
SCU Pad Test Data
Register 0
F000 00B4
H
U, SV U, SV XXXX XXXX
H
SCU_
PTDAT1
SCU Pad Test Data
Register 1
F000 00B8
H
U, SV U, SV XXXX XXXX
H
SCU_
PTDAT2
SCU Pad Test Data
Register 2
F000 00BC
H
U, SV U, SV XXXX 0XXX
H
SCU_
PTDAT3
SCU Pad Test Data
Register 3
F000 00C0
H
U, SV U, SV XXXX XXXX
H
– Reserved F000 00C4
H
-
F000 00C8
H
BE BE –
SCU_
PETCR
SCU Parity Error Trap
Control Register
F000 00D0
H
U, SV U,
SV, E
0000 0000
H
Table 18-3 Address Map of SCU and WDT (cont’d)
Short Name Description Address Access Mode Reset Value
Read Write