Infineon Technologies TC1796

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TC1796

System Units (Vol. 1 of 2)

User’s Manual 18-61 V2.0, 2007-07

Regs, V2.0

DMA_

DADR14

DMA Channel 14

Destination Address

Reg.

F000 3E14

U, SV SV 0000 0000

DMA_

SHADR14

DMA Channel 14

Shadow Address

F000 3E18

U, SV BE 0000 0000

– Reserved F000 3E1C

BE BE –

DMA_

CHSR15

DMA Channel 15 Status

F000 3E20

U, SV BE 0000 0000

DMA_

CHCR15

DMA Channel 15 Control

F000 3E24

U, SV SV 0000 0000

DMA_

CHICR15

DMA Channel 15

Interrupt Control Register

F000 3E28

U, SV SV 0000 0000

DMA_

ADRCR15

DMA Channel 15

Address Control Register

F000 3E2C

U, SV SV 0000 0000

DMA_

SADR15

DMA Channel 15 Source

Address Register

F000 3E30

U, SV SV 0000 0000

DMA_

DADR15

DMA Channel 15

Destination Address

Reg.

F000 3E34

U, SV SV 0000 0000

DMA_

SHADR15

DMA Channel 15

Shadow Address

F000 3E38

U, SV BE 0000 0000

– Reserved F000 3E3C

BE BE –

DMA_

CHSR16

DMA Channel 16 Status

F000 3E40

U, SV BE 0000 0000

DMA_

CHCR16

DMA Channel 16 Control

F000 3E44

U, SV SV 0000 0000

DMA_

CHICR16

DMA Channel 16

Interrupt Control Register

F000 3E48

U, SV SV 0000 0000

DMA_

ADRCR16

DMA Channel 16

Address Control Register

F000 3E4C

U, SV SV 0000 0000

DMA_

SADR16

DMA Channel 16 Source

Address Register

F000 3E50

U, SV SV 0000 0000

Table 18-23 Address Map of DMA (cont’d)

Short Name Description Address Access Mode Reset Value

Read Write

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