Infineon Technologies TC1796

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TC1796

System Units (Vol. 1 of 2)

User’s Manual 18-60 V2.0, 2007-07

Regs, V2.0

DMA_

DADR12

DMA Channel 12

Destination Address

Reg.

F000 3DD4

U, SV SV 0000 0000

DMA_

SHADR12

DMA Channel 12

Shadow Address

F000 3DD8

U, SV BE 0000 0000

– Reserved F000 3DDC

BE BE –

DMA_

CHSR13

DMA Channel 13 Status

F000 3DE0

U, SV BE 0000 0000

DMA_

CHCR13

DMA Channel 13 Control

F000 3DE4

U, SV SV 0000 0000

DMA_

CHICR13

DMA Channel 13

Interrupt Control Register

F000 3DE8

U, SV SV 0000 0000

DMA_

ADRCR13

DMA Channel 13

Address Control Register

F000 3DEC

U, SV SV 0000 0000

DMA_

SADR13

DMA Channel 13 Source

Address Register

F000 3DF0

U, SV SV 0000 0000

DMA_

DADR13

DMA Channel 13

Destination Address

Reg.

F000 3DF4

U, SV SV 0000 0000

DMA_

SHADR13

DMA Channel 13

Shadow Address

F000 3DF8

U, SV BE 0000 0000

– Reserved F000 3DFC

BE BE –

DMA_

CHSR14

DMA Channel 14 Status

F000 3E00

U, SV BE 0000 0000

DMA_

CHCR14

DMA Channel 14 Control

F000 3E04

U, SV SV 0000 0000

DMA_

CHICR14

DMA Channel 14

Interrupt Control Register

F000 3E08

U, SV SV 0000 0000

DMA_

ADRCR14

DMA Channel 14

Address Control Register

F000 3E0C

U, SV SV 0000 0000

DMA_

SADR14

DMA Channel 14 Source

Address Register

F000 3E10

U, SV SV 0000 0000

Table 18-23 Address Map of DMA (cont’d)

Short Name Description Address Access Mode Reset Value

Read Write

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