Infineon Technologies TC1796

To Next Page

To Previous Page

TC1796

System Units (Vol. 1 of 2)

User’s Manual 18-59 V2.0, 2007-07

Regs, V2.0

DMA_

DADR10

DMA Channel 10

Destination Address

Reg.

F000 3D94

U, SV SV 0000 0000

DMA_

SHADR10

DMA Channel 10

Shadow Address

F000 3D98

U, SV BE 0000 0000

– Reserved F000 3D9C

BE BE –

DMA_

CHSR11

DMA Channel 11 Status

F000 3DA0

U, SV BE 0000 0000

DMA_

CHCR11

DMA Channel 11 Control

F000 3DA4

U, SV SV 0000 0000

DMA_

CHICR11

DMA Channel 11

Interrupt Control Register

F000 3DA8

U, SV SV 0000 0000

DMA_

ADRCR11

DMA Channel 11Address

Control Register

F000 3DAC

U, SV SV 0000 0000

DMA_

SADR11

DMA Channel 11 Source

Address Register

F000 3DB0

U, SV SV 0000 0000

DMA_

DADR11

DMA Channel 11

Destination Address

Reg.

F000 3DB4

U, SV SV 0000 0000

DMA_

SHADR11

DMA Channel 11

Shadow Address

F000 3DB8

U, SV BE 0000 0000

– Reserved F000 3DBC

BE BE –

DMA_

CHSR12

DMA Channel 12 Status

F000 3DC0

U, SV BE 0000 0000

DMA_

CHCR12

DMA Channel 12 Control

F000 3DC4

U, SV SV 0000 0000

DMA_

CHICR12

DMA Channel 12

Interrupt Control Register

F000 3DC8

U, SV SV 0000 0000

DMA_

ADRCR12

DMA Channel 12

Address Control Register

F000 3DCC

U, SV SV 0000 0000

DMA_

SADR12

DMA Channel 12 Source

Address Register

F000 3DD0

U, SV SV 0000 0000

Table 18-23 Address Map of DMA (cont’d)

Short Name Description Address Access Mode Reset Value

Read Write

Main Page

Infineon Technologies TC1796 - Page 1048

Table of Contents