Infineon Technologies TC1796

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TC1796

System Units (Vol. 1 of 2)

User’s Manual 18-58 V2.0, 2007-07

Regs, V2.0

DMA_

DADR06

DMA Channel 06

Destination Address

Reg.

F000 3D54

U, SV SV 0000 0000

DMA_

SHADR06

DMA Channel 06

Shadow Address

F000 3D58

U, SV BE 0000 0000

– Reserved F000 3D5C

BE BE –

DMA_

CHSR07

DMA Channel 07 Status

F000 3D60

U, SV BE 0000 0000

DMA_

CHCR07

DMA Channel 07 Control

F000 3D64

U, SV SV 0000 0000

DMA_

CHICR07

DMA Channel 07

Interrupt Control Register

F000 3D68

U, SV SV 0000 0000

DMA_

ADRCR07

DMA Channel 07

Address Control Register

F000 3D6C

U, SV SV 0000 0000

DMA_

SADR07

DMA Channel 07 Source

Address Register

F000 3D70

U, SV SV 0000 0000

DMA_

DADR07

DMA Channel 07

Destination Address

Reg.

F000 3D74

U, SV SV 0000 0000

DMA_

SHADR07

DMA Channel 07

Shadow Address

F000 3D78

U, SV BE 0000 0000

– Reserved F000 3D7C

BE BE –

DMA_

CHSR10

DMA Channel 10 Status

F000 3D80

U, SV BE 0000 0000

DMA_

CHCR10

DMA Channel 10 Control

F000 3D84

U, SV SV 0000 0000

DMA_

CHICR10

DMA Channel 10

Interrupt Control Register

F000 3D88

U, SV SV 0000 0000

DMA_

ADRCR10

DMA Channel 10

Address Control Register

F000 3D8C

U, SV SV 0000 0000

DMA_

SADR10

DMA Channel 10 Source

Address Register

F000 3D90

U, SV SV 0000 0000

Table 18-23 Address Map of DMA (cont’d)

Short Name Description Address Access Mode Reset Value

Read Write

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