Infineon Technologies TC1796

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TC1796

System Units (Vol. 1 of 2)

User’s Manual 18-57 V2.0, 2007-07

Regs, V2.0

DMA_

DADR04

DMA Channel 04

Destination Address

Reg.

F000 3D14

U, SV SV 0000 0000

DMA_

SHADR04

DMA Channel 04

Shadow Address

F000 3D18

U, SV BE 0000 0000

– Reserved F000 3D1C

BE BE –

DMA_

CHSR05

DMA Channel 05 Status

F000 3D20

U, SV BE 0000 0000

DMA_

CHCR05

DMA Channel 05 Control

F000 3D24

U, SV SV 0000 0000

DMA_

CHICR05

DMA Channel 05

Interrupt Control Register

F000 3D28

U, SV SV 0000 0000

DMA_

ADRCR05

DMA Channel 05

Address Control Register

F000 3D2C

U, SV SV 0000 0000

DMA_

SADR05

DMA Channel 05 Source

Address Register

F000 3D30

U, SV SV 0000 0000

DMA_

DADR05

DMA Channel 05

Destination Address

Reg.

F000 3D34

U, SV SV 0000 0000

DMA_

SHADR05

DMA Channel 05

Shadow Address

F000 3D38

U, SV BE 0000 0000

– Reserved F000 3D3C

BE BE –

DMA_

CHSR06

DMA Channel 06 Status

F000 3D40

U, SV BE 0000 0000

DMA_

CHCR06

DMA Channel 06 Control

F000 3D44

U, SV SV 0000 0000

DMA_

CHICR06

DMA Channel 06

Interrupt Control Register

F000 3D48

U, SV SV 0000 0000

DMA_

ADRCR06

DMA Channel 06

Address Control Register

F000 3D4C

U, SV SV 0000 0000

DMA_

SADR06

DMA Channel 06 Source

Address Register

F000 3D50

U, SV SV 0000 0000

Table 18-23 Address Map of DMA (cont’d)

Short Name Description Address Access Mode Reset Value

Read Write

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