Infineon Technologies TC1796 - Page 1079

TC1796
System Units (Vol. 1 of 2)
Register Overview
User’s Manual 18-90 V2.0, 2007-07
Regs, V2.0
ADC0_
CHSTAT9
ADC0 Channel Status
Register 9
F010 0554
H
U, SV U, SV 0000 0000
H
ADC0_
CHSTAT10
ADC0 Channel Status
Register 10
F010 0558
H
U, SV U, SV 0000 0000
H
ADC0_
CHSTAT11
ADC0 Channel Status
Register 11
F010 055C
H
U, SV U, SV 0000 0000
H
ADC0_
CHSTAT12
ADC0 Channel Status
Register 12
F010 0560
H
U, SV U, SV 0000 0000
H
ADC0_
CHSTAT13
ADC0 Channel Status
Register 13
F010 0564
H
U, SV U, SV 0000 0000
H
ADC0_
CHSTAT14
ADC0 Channel Status
Register 14
F010 0568
H
U, SV U, SV 0000 0000
H
ADC0_
CHSTAT15
ADC0 Channel Status
Register 15
F010 056C
H
U, SV U, SV 0000 0000
H
ADC0_
QUEUE0
ADC0 Queue Status
Register
F010 0570
H
U, SV U, SV 0000 0000
H
– Reserved F010 0574
H
-
F010 057C
H
BE BE –
ADC0_
SW0CRP
ADC0 Software SW0
Conversion Request
Pending Register
F010 0580
H
U, SV U, SV 0000 0000
H
– Reserved F010 0584
H
BE BE –
ADC0_
ASCRP
ADC0 Auto Scan
Conversion Request
Pending Register
F010 0588
H
U, SV U, SV 0000 0000
H
– Reserved F010 058C
H
BE BE –
ADC0_
SYSTAT
ADC0 Synchronization
Status Register
F010 0590
H
U, SV U, SV 0000 0000
H
– Reserved F010 0594
H
-
F010 059C
H
BE BE –
– Reserved; these locations
must not be written.
F010 05A0
H
-
F010 05A4
H
nBE nBE –
Table 18-29 Address Map of ADC0/ADC1 (cont’d)
Short Name Description Address Access Mode Reset Value
Read Write