TC1796
System Units (Vol. 1 of 2)
Register Overview
User’s Manual 18-89 V2.0, 2007-07
Regs, V2.0
ADC0_
LCCON3
ADC0 Limit Check Control
Register 3
F010 050C
H
U, SV U, SV 0000 0000
H
– Reserved F010 0510
H
BE BE –
ADC0_
TCON
ADC0 Timer Control
Register
F010 0514
H
U, SV U, SV 0000 0000
H
ADC0_
CHIN
ADC0 Channel Injection
Control Register
F010 0518
H
U, SV U, SV 0000 0000
H
ADC0_QR ADC0 Queue Register F010 051C
H
U, SV U, SV 0000 0000
H
ADC0_CON ADC0 Converter Control
Register
F010 0520
H
U, SV U, SV 0000 0001
H
ADC0_SCN ADC0 Auto Scan Control
Register
F010 0524
H
U, SV U, SV 0000 0000
H
ADC0_
REQ0
ADC0 Conversion
Request Register SW0
F010 0528
H
U, SV U, SV 0000 0000
H
– Reserved F010 052C
H
BE BE –
ADC0_
CHSTAT0
ADC0 Channel Status
Register 0
F010 0530
H
U, SV U, SV 0000 0000
H
ADC0_
CHSTAT1
ADC0 Channel Status
Register 1
F010 0534
H
U, SV U, SV 0000 0000
H
ADC0_
CHSTAT2
ADC0 Channel Status
Register 2
F010 0538
H
U, SV U, SV 0000 0000
H
ADC0_
CHSTAT3
ADC0 Channel Status
Register 3
F010 053C
H
U, SV U, SV 0000 0000
H
ADC0_
CHSTAT4
ADC0 Channel Status
Register 4
F010 0540
H
U, SV U, SV 0000 0000
H
ADC0_
CHSTAT5
ADC0 Channel Status
Register 5
F010 0544
H
U, SV U, SV 0000 0000
H
ADC0_
CHSTAT6
ADC0 Channel Status
Register 6
F010 0548
H
U, SV U, SV 0000 0000
H
ADC0_
CHSTAT7
ADC0 Channel Status
Register 7
F010 054C
H
U, SV U, SV 0000 0000
H
ADC0_
CHSTAT8
ADC0 Channel Status
Register 8
F010 0550
H
U, SV U, SV 0000 0000
H
Table 18-29 Address Map of ADC0/ADC1 (cont’d)
Short Name Description Address Access Mode Reset Value
Read Write
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