TC1796
System Units (Vol. 1 of 2)
Register Overview
User’s Manual 18-88 V2.0, 2007-07
Regs, V2.0
ADC0_
CHCON12
ADC0 Channel Control
Register 12
F010 0440
H
U, SV U, SV 0000 0000
H
ADC0_
CHCON13
ADC0 Channel Control
Register 13
F010 0444
H
U, SV U, SV 0000 0000
H
ADC0_
CHCON14
ADC0 Channel Control
Register 14
F010 0448
H
U, SV U, SV 0000 0000
H
ADC0_
CHCON15
ADC0 Channel Control
Register 15
F010 044C
H
U, SV U, SV 0000 0000
H
– Reserved F010 0450
H
-
F010 0480
H
BE BE –
ADC0_AP ADC0 Arbitration
Participation Register
F010 0484
H
U, SV U, SV 0000 0000
H
ADC0_SAL ADC0 Source Arbitration
Level Register
F010 0488
H
U, SV U, SV 0103 4067
H
ADC0_TTC ADC0 Timer Trigger
Control Register
F010 048C
H
U, SV U, SV 0000 0000
H
ADC0_
EXTC
ADC0 External Trigger
Control Register
F010 0490
H
U, SV U, SV 0000 0000
H
– Reserved F010 0494
H
BE BE –
ADC0_
SCON
ADC0 Source Control
Register
F010 0498
H
U, SV U, SV 0000 0000
H
– Reserved F010 049C
H
BE BE –
– Reserved; these locations
must not be written.
F010 04A0
H
-
F010 04DC
H
nBE nBE –
– Reserved F010 04E0
H
-
F010 04FC
H
BE BE –
ADC0_
LCCON0
ADC0 Limit Check Control
Register 0
F010 0500
H
U, SV U, SV 0000 0000
H
ADC0_
LCCON1
ADC0 Limit Check Control
Register 1
F010 0504
H
U, SV U, SV 0000 0000
H
ADC0_
LCCON2
ADC0 Limit Check Control
Register 2
F010 0508
H
U, SV U, SV 0000 0000
H
Table 18-29 Address Map of ADC0/ADC1 (cont’d)
Short Name Description Address Access Mode Reset Value
Read Write
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