TC1796
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
User’s Manual 19-15 V2.0, 2007-07
ASC, V2.0
Using the Fractional Divider
When the fractional divider is selected, the input clock f
DIV
for the baud rate timer is
derived from the module clock f
ASC
by a programmable fractional divider. If
CON.FDE = 1, the fractional divider is activated. It divides f
ASC
by a fraction of n/512 for
any value of n from 0 to 511. If n = 0, the divider ratio is 1, which means that f
DIV
= f
ASC
.
In general, the fractional divider allows the baud rate to be programmed with much better
accuracy than with the two fixed prescaler divider stages.
Note: In fractional divider mode, the clock f
DIV
can have a maximum period jitter of one
f
ASC
clock period.
BG represents the content of the reload register bit field BG.BR_VALUE, taken as an
unsigned 13-bit integer. FDV represents the contents of the fractional divider register bit
field FDV.FD_VALUE, taken as an unsigned 9-bit integer.
Table 19-3 Asynchronous Baud Rate Formulas using the Fractional Input Clock
Divider
FDE BRS BG FDV Formula
1 – 0 … 8191 1 … 511
0
Table 19-4 Typical Asynchronous Baud Rates using the Fractional Input Clock
Divider
f
ASC
Desired
Baud Rate
BG FDV Resulting
Baud Rate
Deviation
75 MHz 115.2 kbit/s 17
H
12E
H
115.204 kbit/s < 0.01%
57.6 kbit/s 2F
H
12E
H
57.602 kbit/s < 0.01%
38.4 kbit/s 23
H
097
H
38.401 kbit/s < 0.01%
19.2 kbit/s AE
H
16F
H
19.200 kbit/s < 0.01%
Baud rate
FDV
512
------------
f
ASC
16 BG 1+()×
------------------------------------
×=
Baud rate
f
ASC
16 BG 1+()×
------------------------------------=
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