Infineon Technologies TC1796 - Page 1129

TC1796
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
User’s Manual 19-14 V2.0, 2007-07
ASC, V2.0
Using the Fixed Input Clock Divider
The baud rate for asynchronous operation of the serial channel ASC when using the
fixed input clock divider ratios (CON.FDE = 0) and the required BG reload value for a
given baud rate can be determined by the following formulas:
BG represents the content of the reload register bit field BG.BR_VALUE, taken as an
unsigned 13-bit integer.
The maximum baud rate that can be achieved for the asynchronous operating modes
when using the two fixed clock dividers and a module clock of 75 MHz is 2.34 Mbit/s.
Table 19-2 lists various commonly used baud rates together with the required reload
values and the deviation errors compared to the intended baud rate.
Note: CON.FDE must be 0 to achieve the baud rates in the table above. The deviation
errors given in the table are rounded. Using a baud rate crystal will provide correct
baud rates without deviation errors.
Table 19-1 Asynchronous Baud Rate Formulas using the Fixed Input Clock
Dividers
FDE BRS BG Formula
0 0 0 … 8191
1
Table 19-2 Typical Asynchronous Baud Rates using Fixed Input Clock Dividers
Baud Rate CON.BRS = 0, f
ASC
= 75 MHz CON.BRS = 1, f
ASC
= 75 MHz
Deviation Error Reload Value Deviation Error Reload Value
2.344 Mbit/s – 0000
H
––
19.2 kbit/s +0.1% / -0.8% 0079
H
/ 007A
H
+0.5% / -0.8% 0050
H
/ 0051
H
9600 bit/s +0.1% / -0.4% 00F3
H
/ 00F4
H
+0.5% / -0.1% 00A1
H
/ 00A2
H
4800 bit/s +0.1% / -0.2% 01E7
H
/ 01E8
H
+0.2% / -0.1% 0144
H
/ 0145
H
Baud rate
f
ASC
32 BG 1+()×
------------------------------------=
BG
f
ASC
32 Baud rate×
---------------------------------------
1–=
Baud rate
f
ASC
48 BG 1+()×
-------------------------------------=
BG
f
ASC
48 Baud rate×
---------------------------------------
1–=