TC1796
Peripheral Units (Vol. 2 of 2)
Synchronous Serial Interface (SSC)
User’s Manual 20-23 V2.0, 2007-07
SSC, V2.1
Slave Select Output 7 Delayed Mode
In the SLSO7 delayed mode (SSOTC.SLSO7MOD = 1), the timing of the slave select
output SLSO7 as programmed by the three parameters in SSOTC (number of trailing,
leading, and inactive delay clock cycles) is delayed by one shift clock period for the
inactive-to-active edge. The active-to-inactive edge is not delayed. The timing of SLSO7
in the delayed mode is shown in Figure 20-13. The bold lines show the timing of SLSO7
in normal operating mode, and the dotted lines show the timing of SLSO7 in delayed
mode.
Figure 20-13 SLSO7 Delayed Mode
Slave Select Register Update
At the start of an internal transmit sequence (with the TB register write operation), the
parameters in registers SSOC and SSOTC are buffered. This means that they remain
stable while a serial transmission is in progress. Therefore, it is always guaranteed that
the data of one serial transmission is always transmitted with a constant slave select
configuration setup. A configuration change by reprogramming SSOC or SSOTC during
a serial transmission will first become valid with the start of the subsequent serial
transmission.
MCT05788
SCLK
SLSO7 with
LEAD = 11
B
Data Frame
SLSO7 with
LEAD = 10
B
SLSO7 with
LEAD = 01
B
SLSO7 with
LEAD = 00
B
t
SLSOACT
Note: The timing is valid for clock polarity control bit CON.PO = 1.
To Next Page
Loading...
Need help?
General