TC1796
Peripheral Units (Vol. 2 of 2)
Synchronous Serial Interface (SSC)
User’s Manual 20-33 V2.0, 2007-07
SSC, V2.1
LB 7rwLoop-Back Control
0
B
Normal output
1
B
Receive input is connected to transmit output
(Half-duplex Mode)
TEN 8rwTransmit Error Enable
0
B
Ignore transmit errors
1
B
Check transmit errors
REN 9rwReceive Error Enable
0
B
Ignore receive errors
1
B
Check receive errors
PEN 10 rw Phase Error Enable
0
B
Ignore phase errors
1
B
Check phase errors
BEN 11 rw Baud Rate Error Enable
0
B
Ignore baud rate errors
1
B
Check baud rate errors
AREN 12 rw Automatic Reset Enable
0
B
No additional action upon a baud rate error
1
B
SSC is automatically reset on a baud rate error
MS 14 rw Master Select
0
B
Slave Mode. Operate on shift clock received via
SCLK
1
B
Master Mode. Generate shift clock and output it
via SCLK
The inverted state of this bit is available on module
output line “M/S selected” (see Figure 20-2).
EN 15 rw Enable Bit
0
B
Transmission and reception are disabled.
1
B
Transmission and reception are enabled.
This bit is available as module output line “SSC
enabled” (see Figure 20-2). Note that EN should only
be cleared by software while no transfer is in progress
(STAT.BSY = 0).
0 13,
[31:16]
r Reserved
Read as 0; should be written with 0.
Field Bits Type Description
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